The present invention relates generally to integrated circuits, and in particular to memory devices having delay locked loop circuits.
Delay locked loop (DLL) circuits reside in many memory devices to receive an external signal to generate an internal signal. The DLL automatically keeps the internal signal synchronized with the external signal. The internal signal usually serves as a reference signal for the memory devices instead of the external signal because the internal signal matches internal operating conditions of the memory devices, such as process, voltage, and temperature, better than the external signal does.
A typical memory device has many memory cells to store data. The memory device writes data into the memory cells during a write mode and reads the data stored in the memory cells during a read mode. The memory device also has other modes of operations.
In some modes of operations, the memory device uses the internal clock signal generated by the DLL. In other modes of operations, the internal clock signal is unused. Therefore, keeping the DLL active all the time wastes power.
Various embodiments of the invention provide circuits and methods to periodically deactivate a DLL in certain modes of operations of a memory device.
In one aspect, the memory device includes a plurality of memory banks for storing data and a clock path for receiving an external signal to generate an internal signal to control a transfer of the data from the memory banks. The clock path includes a delay locked loop for synchronizing the external and internal signals. The memory device also includes a clock path controller for periodically deactivating the delay locked loop in response to modes of operations of the memory device.
In another aspect, a method of operating a memory device includes generating an internal signal based on an external signal. The method further includes partially deactivating the internal signal within each cycle of a periodic signal when the memory device is in certain modes of operations.